1. Field of the Invention
The present invention relates to semiconductor integrated circuits for converting data constituted in block units (hereinafter referred to as block data) into raster data. Particularly, the present invention relates to a technique suitable for the so-called next-generation digital television in multimedia. The present invention is, of course, also applicable to fields other than the next-generation digital television.
2. Description of the Background Art
The techniques for realizing the block-raster conversion/inverse conversion with a small-scale circuit include that disclosed in Japanese Patent Laying-Open No. 8-171384, for example. In this technique, with an address provided to a block buffer, reading operation is made in the first half and data is written into the free area caused by the reading. This reduces the number of the block buffers from two to one and also enables simply structured calculation of the access addresses.
However, the conventional block/raster converting technique is adaptable only to one particular video format. For example, the above-mentioned conventional converting technique (Japanese Patent Laying-Open No. 8-171384) is adaptable only to NTSC standard for television broadcasting, whose objects are size reduction of a block/raster converting circuit and size reduction of the memory capacity with a particular format.
However, the next-generation digital television (advanced TV) which performs a part of the recent improvements in multimedia technique requires a circuit which converts MPEG2 standard block data into raster data. Furthermore, since it handles video sources of various formats (or the number of macro-blocks), it is necessary to develop a converting circuit which is adaptable to all of the formats. The conventional technique can not deal with such new technical problems.
According to a first aspect of the present invention, a semiconductor integrated circuit for converting macro-block data into raster data comprises: a memory; and memory control means for controlling mapping of the macro-block data of an arbitrary format among a plurality of formats into the memory on the basis of mapping in the case of a particular format having a maximum data size in a horizontal direction among the plurality of formats.
Preferably, according to a second aspect, in the semiconductor integrated circuit of the first aspect, the memory comprises a memory region including maximum macro-block row regions into each of which the macro-block data included in each of a plurality of maximum macro-block rows can be mapped, the plurality of maximum macro-block rows each having a region determined on the basis of the data size of the particular format in the horizontal direction and in a vertical direction, and the memory control means comprises mapping control means for mapping the macro-block data of the arbitrary format, for each macro-block row whose region is determined on the basis of the data size of the arbitrary format, into one of the maximum macro-block row regions corresponding to that macro block row, according to a data array of a plurality of macro-blocks belonging to that macro-block row.
Preferably, according to a third aspect, in the semiconductor integrated circuit of the second aspect, the mapping control means comprises address generating means for, for each macro-block row of the arbitrary format, specifying an address of the macro-block data at the head of an initial macro-block belonging to that macro-block row as initial data in corresponding one of the maximum macro-block row regions, on the basis of which address the address generating means generating addresses of the macro-block data belonging to that macro-block row in accordance with the data array and outputting the obtained address signal to the memory.
Preferably, according to a fourth aspect, in the semiconductor integrated circuit of the third aspect, the memory control means further comprises data read control means for, for each macro-block row of the arbitrary format, specifying a row address and a column address of the address of the initial macro-block data belonging to that macro-block row, switching the column address on the basis of the address of the initial macro-block data, and switching the row address when the macro-block data belonging to a line in the horizontal direction belonging to that macro-block row has been all read and when the macro-block data written in an address at a turn of each of the maximum macro-block row regions has been read, thereby reading data from the memory region.
Preferably, according to a fifth aspect, in the semiconductor integrated circuit of the fourth aspect, the memory region comprises first and second memory regions, and the address generating means comprises (a) means for mapping the macro-block data belonging to odd lines in the horizontal direction in the macro-block into the first memory region, and (b) means for mapping the macro-block data belonging to even lines in the horizontal direction in the macro-block into the second memory region.
Preferably, according to a sixth aspect, in the semiconductor integrated circuit of the fourth aspect, the memory comprises, as the memory region, first and second memory regions separated into two in its bit direction, and the address generating means comprises pre-processing means for pre-processing the sequentially inputted macro-block data into bus data having odd line data formed of the macro-block data belonging to odd lines in the horizontal direction in the macro-block and even line data formed of the macro-block data belonging to even lines in the horizontal direction each corresponding to the line next to each of the odd lines in the horizontal direction, and means for mapping the odd line data and the even line data into-the first and second memory regions, respectively.
Preferably, according to a seventh aspect, in the semiconductor integrated circuit of the sixth aspect, the data read control means comprises means for simultaneously reading the odd line data and the even line data corresponding thereto as the bus data, wherein the semiconductor integrated circuit further comprises post-processing means for applying certain post-processing to the read bus data to output the raster data having a certain output format.
Preferably, according to an eighth aspect, the semiconductor integrated circuit of the fourth aspect further comprises precharge means for regularly precharging the memory region in accordance with a format having a minimum timing for switching the row address when reading the macro-block data.
Preferably, according to a ninth aspect, in the semiconductor integrated circuit of the second aspect, the mapping control means comprises address generating means for, for each macro-block row of the arbitrary format, specifying an address of the macro-block data at the end belonging to that macro-block row as final data in corresponding one of the maximum macro-block row regions, and determining an address of the macro-block data at the head of an initial macro-block belonging to that macro-block row on the basis of a difference between the data size of the particular format in the horizontal direction and the data size of the arbitrary format in the horizontal direction, thereby generating an address signal for the macro-block data belonging to that macro-block row and outputting the address signal to the memory.
Preferably, according to a tenth aspect, in the semiconductor integrated circuit of the ninth aspect, the memory control means further comprises data read control means for, for each macro-block row of the arbitrary format, specifying a row address and a column address of the address of the initial macro-block data belonging to that macro-block row, sequentially switching the column address on the basis of the address of the initial macro-block data, and switching the row address when the macro-block data belonging to a line in the horizontal direction belonging to that macro-block row has been all read and when the macro-block data written in an address at a turn of each of the maximum macro-block row regions has been read, thereby reading data from the memory region.
Preferably, according to an eleventh aspect, in the semiconductor integrated circuit of the tenth aspect, the memory region comprises first and second memory regions, and the address generating means comprises (a) means for mapping the macro-block data belonging to odd lines in the horizontal direction in the macro-block into the first memory region, and (b) means for mapping the macro-block data belonging to even lines in the horizontal direction in the macro-block into the second memory region.
Preferably, according to a twelfth aspect, in the semiconductor integrated circuit of the tenth aspect, the memory comprises, as the memory region, first and second memory regions separated into two in its bit direction, and the address generating means comprises pre-processing means for pre-processing the sequentially inputted macro-block data into bus data having odd line data formed of the macro-block data belonging to odd lines in the horizontal direction in the macro-block and even line data formed of the macro-block data belonging to even lines in the horizontal direction each corresponding to the line next to each of the odd lines in the horizontal direction, and means for mapping the odd line data and the even line data into the first and second memory regions, respectively.
Preferably, according to a thirteenth aspect, in the semiconductor integrated circuit of the twelfth aspect, the data read control means comprises means for simultaneously reading the odd line data and the even line data corresponding thereto as the bus data, wherein the semiconductor integrated circuit further comprises post-processing means for applying certain post-processing to the read bus data to output the raster data having a certain output format.
Preferably, according to a fourteenth aspect, the semiconductor integrated circuit of the tenth aspect further comprises precharge means for regularly precharging the memory region in accordance with a format having a minimum timing for switching the row address when reading the macro-block data.
According to a fourteenth aspect, a semiconductor integrated circuit comprises: a macro-block data signal input line for inputting macro-block data; and a memory connected to the macro-block data signal input line, and into which the macro-block data of an arbitrary format among a plurality of formats is mapped on the basis of mapping in the case of a particular format having a maximum data size in its horizontal direction among the plurality of formats.
According to a sixteenth aspect, a semiconductor integrated circuit comprises: a clock signal input line for inputting a clock and a macro-block data signal input line for inputting a plurality of macro-block data related to a certain format among a plurality of formats for each macro-block on the basis of the clock; a memory control signal input line for inputting a memory control signal for controlling timing of writing and reading data; an address generating circuit connected to the clock signal input line and the memory control signal input line, for generating addresses for mapping the macro-block data related to the certain format on the basis of mapping of the plurality of macro-block data related to a particular format having a maximum data size in its horizontal direction among the plurality of formats in accordance with the clock and the memory control signal; and a memory connected to the macro-block data signal input line, the clock signal input line, the memory control signal input line and an output line of the address generating circuit, and into which the plurality of macro-block data are written on the basis of the memory control signal and the addresses.
According to the first to third, ninth, and fifteenth and sixteenth aspects, mapping can be done with the same circuit even with different formats, which enables mapping as preparations for block-to-raster conversion with the same circuit.
Particularly, according to the ninth aspect, it is possible to realize area reduction of the circuit.
According to the fourth and tenth aspects, since raster data can always be read irrespective of the format, it is easy to apply block-to-raster conversion to each of various formats.
According to the fifth and eleventh aspects, all macro-block data to be converted can be mapped separately as odd line data and even line data. Accordingly, (1) the odd line data and the even line data can be independently outputted, or (2) one of the odd line data and the even line data can be repeatedly outputted, providing various and easy-to-change output formats of raster data.
According to the sixth and twelfth, and seventh and thirteenth aspects, (1) the odd line data and the even line data can be independently outputted, (2) the odd line data and the even line data can be simultaneously outputted, or (3) one of the odd line data and the even line data can be repeatedly outputted, easily enabling a more variety of output formats.
According to the eighth and fourteenth aspects, precharge can be done with a common circuit which is independent of the format.
The present invention has been made to solve the above-described problem. Its first object is to realize block data/raster data conversion adaptable to a plurality of formats with the same device. The present invention provides various novel mapping techniques for this purpose.
A second object of the present invention is to enable a single circuit to easily output raster data of different output formats.
Furthermore, a third object of the present invention is to enable precharging of a memory which is independent of input/output formats.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.